Facilitating FPGA Reconfiguration through Low-level Manipulation

Simple item page
dc.contributor.authorZha, Wenweien
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.committeememberSchaumont, Patrick R.en
dc.contributor.committeememberSun, Shu Mingen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-25T08:00:46Zen
dc.date.available2014-03-25T08:00:46Zen
dc.date.issued2014-03-24en
dc.description.abstractThe process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how hardware is compiled for achieving high performance, which requires a long computation time. How to efficiently compile a design becomes the bottleneck for FPGA reconfiguration. It is promising to apply some techniques or concepts from software to facilitate FPGA reconfiguration. This dissertation explores such an idea by utilizing three types of low-level manipulation on FPGA logic and routing resources, i.e. relocating, mapping/placing, and routing. It implements an FMA technique for "fast reconfiguration". The FMA makes use of the software compilation technique of reusing pre-compiled libraries for explicitly reducing FPGA compilation time. Based the software concept of Autonomic Computing, this dissertation proposes to build an Autonomous Adaptive System (AAS) to achieve "self-reconfiguration". An AAS absorbs the computing complexity into itself and compiles the desired change on its own. For routing, an FPGA router is developed. This router is able to route the MCNC benchmark circuits on five Xilinx devices within 0.35 ~ 49.05 seconds. Creating a routing-free sandbox with this router is 1.6 times faster than with OpenPR. The FMA uses relocating to load pre-compiled modules and uses routing to stitch the modules. It is an essential component of TFlow, which achieves 8 ~ 39 times speedup as compared to the traditional ISE flow on various test cases. The core part of an AAS is a lightweight embedded version of utilities for managing the system's hardware functionality. Two major utilities are mapping/placing and routing. This dissertation builds a proof-of-concept AAS with a universal UART transmitter. The system autonomously instantiates the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver.en
dc.description.degreePh. D.en
dc.format.mediumETDen
dc.identifier.othervt_gsexam:2341en
dc.identifier.urihttp://hdl.handle.net/10919/46787en
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGA Reconfigurationen
dc.subjectBitstream-level Manipulationen
dc.subjectFPGA Routingen
dc.subjectModule Reuseen
dc.subjectDesign Assemblyen
dc.subjectAutonomous Adaptive Systemsen
dc.subjectElectronic Design Automationen
dc.titleFacilitating FPGA Reconfiguration through Low-level Manipulationen
dc.typeDissertationen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

Files

Original bundle
Now showing 1 - 3 of 3
Thumbnail Image
Name:
Zha_W_D_2014.pdf
Size:
2.53 MB
Format:
Adobe Portable Document Format
Download
Thumbnail Image
Name:
Zha_W_D_2014_support_3.pdf
Size:
316.39 KB
Format:
Adobe Portable Document Format
Description:
Supporting documents
Download
Thumbnail Image
Name:
Zha_W_D_2014_support_6.pdf
Size:
61.58 KB
Format:
Adobe Portable Document Format
Description:
Supporting documents
Download

Collections

Doctoral Dissertations