An Algorithm for multi-output Boolean logic minimization

dc.contributor.authorVora, Rohit H.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:40:54Zen
dc.date.adate2010-07-21en
dc.date.available2014-03-14T21:40:54Zen
dc.date.issued1987en
dc.date.rdate2010-07-21en
dc.date.sdate2010-07-21en
dc.description.abstractA new algorithm is presented for a guaranteed absolute minimal solution to the problem of Boolean Logic Minimization in its most generalized form of multi-output function with arbitrary cost criterion. The proposed algorithm is shown to be tighter than the Quine-McCluskey method in its ability to eliminate redundant prime implicants, making it possible to simplify the cyclic tables. In its final form, the proposed algorithm is truly concurrent in generation of prime implicants and construction of minimal forms. A convenient and efficient technique is used for identifying existing prime implicants. Branch-and-bound method is employed to restrict the search tree to a cost cut-off value depending on the definition of cost function specified. A most generalized statement of the algorithm is formulated for manual as well as computer implementation and its application is illustrated with an example. A program written in Pascal, for classical diode-gate cost function as well as PLA-area cost function, is developed and tested for an efficient computer implementation. Finally, various advantages of the proposed approach are pointed out by comparing it with the classical approach of Quine-McCluskey method.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 165 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-07212010-020151en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07212010-020151/en
dc.identifier.urihttp://hdl.handle.net/10919/43829en
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1987.V672.pdfen
dc.relation.isformatofOCLC# 16906888en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1987.V672en
dc.subject.lcshAlgebra, Booleanen
dc.subject.lcshAlgorithmsen
dc.subject.lcshSwitching circuitsen
dc.titleAn Algorithm for multi-output Boolean logic minimizationen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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