Model based approach to Hardware/ Software Partitioning of SOC Designs

dc.contributor.authorAdhipathi, Pradeepen
dc.contributor.committeechairBaker, James M. Jr.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2011-08-06T16:02:13Zen
dc.date.adate2004-07-07en
dc.date.available2011-08-06T16:02:13Zen
dc.date.issued2003-12-04en
dc.date.rdate2004-07-07en
dc.date.sdate2004-06-25en
dc.description.abstractAs the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage of the design and then iteratively refining it until a good solution is found. This method is expensive and time consuming. A more modern approach is to model the whole system and rigorously test and refine it before the partitioning is done. The key to this method is the ability to model and simulate the entire system. The advent of new System Level Modeling Languages (SLML), like SystemC, has made this possible. This research proposes a strategy to automate the process of partitioning a system model after it has been simulated and verified. The partitioning idea is based on systems modeled using Process Model Graphs (PmG). It is possible to extract a PmG directly from a SLML like SystemC. The PmG is then annotated with additional attributes like IO delay and rate of activation. A complexity heuristic is generated from this information, which is then used by a greedy algorithm to partition the graph into different architectures. Further, a command line tool has been developed that can process textually represented PmGs and partition them based on this approach.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-06252004-201429en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06252004-201429en
dc.identifier.urihttp://hdl.handle.net/10919/9986en
dc.publisherVirginia Techen
dc.relation.haspartthesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjecthardware modelingen
dc.subjectpartitioningen
dc.subjectsystem on chipen
dc.subjectco-designen
dc.titleModel based approach to Hardware/ Software Partitioning of SOC Designsen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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