Designing FET based multiple valued logic circuits
| dc.contributor.author | Thakar, Anjaneya V. | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2018-03-26T19:54:11Z | en |
| dc.date.available | 2018-03-26T19:54:11Z | en |
| dc.date.issued | 1982 | en |
| dc.description.abstract | The thesis presents an analysis of FET based Multiple Valued Logic circuits. The circuit analysis program SPICE2 was used to analyze these circuits. A description of device modelling as done by SPICE2 is included in the beginning of the thesis. Techniques to implement MVL circuits using simple threshold circuits as building blocks are outlined. The two principal methods of achieving different switching voltages, namely, changing the device threshold and the device transconductance, for these threshold circuits are discussed. A comparative study of these two methods from a theoretical and practical viewpoint is included. Several MOSFET based MVL circuits are developed and an explanation of their operation is also given. | en |
| dc.description.degree | Master of Science | en |
| dc.format.extent | viii, 98 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/82662 | en |
| dc.language.iso | en_US | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 8890685 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1982.T524 | en |
| dc.subject.lcsh | Logic circuits | en |
| dc.title | Designing FET based multiple valued logic circuits | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
Files
Original bundle
1 - 1 of 1