Overloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimation

dc.contributor.authorBayram, Saffeten
dc.contributor.committeechairReed, Jeffrey H.en
dc.contributor.committeememberBoyle, Robert J.en
dc.contributor.committeememberWoerner, Brian D.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:49:13Zen
dc.date.adate2000-12-11en
dc.date.available2014-03-14T20:49:13Zen
dc.date.issued2000-12-08en
dc.date.rdate2001-12-11en
dc.date.sdate2000-12-10en
dc.description.abstractIn airborne communication systems such as airborne cell-extender repeaters the receiver faces the challenge of demodulating the signal of interest (SOI) in the presence of excessive amounts of Co-Channel Interference (CCI) from a large number of sources. This results in the overloaded environment where the number of near-equal power co-channel interferers exceeds the number of antenna array elements. This thesis first analyzes the interference environment experienced by an airborne cellular repeater flying at high altitudes. Link budget analysis using a two-ray propagation model shows that the antenna array mounted on an airborne receiver has to recover the SOI out of hundreds of co-channel interfering signals. This necessitates use of complex overloaded array signal processing techniques. An extensive literature survey on narrowband signal extraction algorithms shows that joint detection schemes, coupled with antenna arrays, provide a solution for narrowband overloaded array problem where as traditional beamforming techniques fail. Simulation results in this thesis investigates three "promising" overloaded array processing algorithms, Multi-User Decision Feedback Equalizer (MU-DFE), Iterative Least Squares with Projection (ILSP), and Iterative Least Squares with Enumeration (ILSE). ILSE is a non-linear joint maximum-likelihood detector, is shown to demodulate many more signals than elements even when the users are closely spaced and the channel is blindly estimated. Multi-user time delay estimation is one of the most important aspects of channel estimation for overloaded array processing. The final chapter of the thesis proposes a low-complexity data-aided time-delay estimation structure for embedding in a Per Survivor Processing (PSP) trellis for overloaded array processing. An extensive analysis proves that the multi-user delay estimation is separable, which leads to the proposed multi-user algorithm that estimates the user delays with a bank of simple data-aided synchronization loops to reduce the complexity. This thesis shows simulation results for the single-user case where the low-complexity Delay Locked Loop (DLL) structure, working at a low oversampling rate of 2 samples per symbol, estimates and compensates for any integer or non-integer sample delay within ±Tsym(symbol period). Two extensions to this technique are proposed to provide efficient multi-user delay estimation. The first multi-user structure employs a bank of DLLs, which compensate for the timing offset of each user simultaneously. This multi-user algorithm is suitable for CDMA-type applications, where each user has a distinct PN-code with good auto- and cross-correlation properties. We show that for spreading gain of 31, the presence of an interpolator enables us to reduce the oversampling factor from 4 to 2 samples per chip. Thus, the requirements of the A/D converter are relaxed without sacrificing system performance. Furthermore, we show that the proposed scheme meets the requirements of multi-user interference cancellation techniques for residual worst-case timing errors, i.e., residual timing error < 0.2 Tc, as reported in [200]. Finally, the thesis recommends a similar multi-user structure for narrowband TDMA-type system, which is based on bank of DLLs with whitening pre-filters at the front end of each branch.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-12102000-183343en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12102000-183343/en
dc.identifier.urihttp://hdl.handle.net/10919/36039en
dc.publisherVirginia Techen
dc.relation.haspartthesis_etd1.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectJoint Detectionen
dc.subjectInterference Mitigationen
dc.subjectAntenna Arrayen
dc.subjectOverloaded Arrayen
dc.titleOverloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimationen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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