Lattice Matched Germanium-on-AlAs Nanosheet-FETs for More-Moore CMOS

Abstract

In this work, the lattice matched germanium (Ge)-on-AlAs-based n-channel nanosheet field effect transistor (NSFET) at subnanometer nodes and their circuit performances were analyzed using calibrated TCAD solvers and benchmarked with comparable devices. This epitaxial monolithic stack offers benefits, such as lower defects and improved reliability due to lattice matching between Ge and AlAs, higher number of nanosheets (NSs), improved selectivity between the channel and sacrificial barriers, and material advantages, such as mobility offered by the Ge channel. The large etch selectivity between the Ge channel and the AlAs sacrificial layer can provide process simplicity, improvements in yield, and reduced impact of potential inter-NS electrical shorts due to incomplete etch. The number of NS layers (one–eight layers), channel length, and widths were studied to predict performance metrics, such as ON- and OFF-current, subthreshold slope (SS), and transconductance. The ON-current was increased from ∼250 to 950 µA/µm by NS scaling from one to eight layers with no increase in area or SS (∼68 mV/dec) at 0.5-V supply voltage. This Ge NSFET is used to form a CMOS inverter to operate at a frequency of ∼100 THz for one, three, and eight NS layers. Ge NSFET-based 6T SRAM circuit performance for different NS layers demonstrated good static noise margins and delays even at these scaled nodes.

Description

Keywords

CMOS, germanium (Ge), Ge-on-AlAs, lattice matched nanosheet (NS), nanosheet FET (NSFET), NSFET process, NSFET SRAM, GAAS, GE

Citation