Support for Send-and-Receive Based Message-Passing for the Single-Chip Message-Passing Architecture

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dc.contributor.authorLewis, Charles William Jr.en
dc.contributor.committeechairBaker, James M. Jr.en
dc.contributor.committeememberArthur, James D.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:34:37Zen
dc.date.adate2004-05-06en
dc.date.available2014-03-14T20:34:37Zen
dc.date.issued2004-04-28en
dc.date.rdate2004-05-06en
dc.date.sdate2004-04-30en
dc.description.abstractArguably, from the programmer's perspective, the programming model is the most important characteristic of any computer system. Perhaps this explains why, after many decades of research, architects and programmers alike continue to debate the appropriate programming model for parallel computers. Though thousands of programming models have been developed, standards such as PVM and MPI have made send-and-receive based message-passing the most popular programming model for distributed memory architectures. This thesis explores modifying the Single-Chip Message-Passing (SCMP) architecture to more efficiently support send-and-receive based message-passing. The proposed system is compared, for performance and programmability, to the active messaging programming model currently used by SCMP. SCMP offers a unique platform for send-and-receive based message-passing. The SCMP design incorporates multiple multi-threaded processors, memory, and a network onto a single chip. This integration reduces the penalties of thread switching, memory access, and inter-process communication typically seen on more traditional distributed memory parallel machines. The mechanisms proposed in this thesis to support send-and-receive based message-passing on SCMP attempt to preserve and exploit these features as much as possible.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-04302004-104254en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-04302004-104254/en
dc.identifier.urihttp://hdl.handle.net/10919/32049en
dc.publisherVirginia Techen
dc.relation.haspartcwl_thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSingle-Chip Computeren
dc.subjectParallel Computingen
dc.subjectMessage-Passingen
dc.titleSupport for Send-and-Receive Based Message-Passing for the Single-Chip Message-Passing Architectureen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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