Fast generation of Gaussian and Laplacian image pyramids using an FPGA-based custom computing platform

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dc.contributor.authorChen, Lunaen
dc.contributor.committeechairAbbott, A. Lynnen
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:50:59Zen
dc.date.adate2009-12-04en
dc.date.available2014-03-14T21:50:59Zen
dc.date.issued1994-09-12en
dc.date.rdate2009-12-04en
dc.date.sdate2009-12-04en
dc.description.abstractThis thesis describes the implementation of a system that can generate two types of image pyramids: the Gaussian pyramid and the Laplacian pyramid. These have been developed using the SPLASH II attached processor, which is a reconfigurable platform based on Field Programmable Gate Arrays (FPGA). The design was first modeled in VHDL, and was then simulated and synthesized to a gate list using a SPLASH II simulator and the Synopsys synthesis tool. The gate list was then mapped onto Xilinx XC4010 FPGA architectures. Three complete designs have been developed to generate pyramids on SPLASH II: two for generating the Gaussian pyramid, and one for generating the Laplacian pyramid. One of the designs produces a complete image pyramid within one image frame time of 33 ms. The other two designs produce complete pyramids within two frame times. All three designs can be used as pipeline stages within a larger image processing system.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 120 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-12042009-020239en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12042009-020239/en
dc.identifier.urihttp://hdl.handle.net/10919/46106en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1994.C5465.pdfen
dc.relation.isformatofOCLC# 31594040en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1994.C5465en
dc.subject.lcshField programmable gate arraysen
dc.subject.lcshImage processingen
dc.titleFast generation of Gaussian and Laplacian image pyramids using an FPGA-based custom computing platformen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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