Design and Evaluation of a Memory-Centric Binary Hyperdimensional Computing Architecture with 1T3R Memristor-Based Nonvolatile Storage

Abstract

Hyperdimensional computing (HDC) represents information with high-dimensional distributed hypervectors and performs classification using simple binary operations such as binding, bundling, and associative search. While these operations are hardware-friendly, the large hypervector dimension creates a substantial persistent-memory and data-movement burden because position/identifier (ID), level, and trained class hypervectors all scale linearly with dimension D. This thesis develops and evaluates a memory-centric Binary HDC architecture for the Modified National Institute of Standards and Technology (MNIST) handwritten-digit dataset. Persistent binary hypervectors are mapped to nonvolatile one-transistor/three-resistor (1T3R) memristor storage, while nearby complementary metal-oxide-semiconductor (CMOS) circuitry performs exclusive OR (XOR) binding, bundling, majority thresholding, Hamming-distance accumulation, and class selection. A controlled design-space study isolates the effects of input resolution, model adjustment, quantization, and hypervector dimension. The selected Balanced D = 5,000 configuration achieves 86.87% validation accuracy and 87.74% accuracy on the official MNIST test set after model freeze. The hardware mapping treats the three memristors in each 1T3R row as three independent HDC dimensions rather than one signed 3-bit coefficient. For the frozen full-resolution, M = 32 configuration, persistent storage scales as 826D logical bits, with the ID bank accounting for approximately 94.9% of capacity. Under a direct-access baseline without caching, one query requires 1,578D logical persistent-bit reads. Measured level usage also reveals an idealized within-query Level-hypervector reuse opportunity that could reduce persistent read traffic by approximately 47.95% with suitable local buffering. Circuit evidence is obtained from the existing SkyWater 130 nm 4 × 3 schematic proof of concept. Experiment 8 (EXP8) verifies all eight Row 1 three-bit states and all 24 static bit decisions, while selective SET of G2, G1, and G0 preserves all observed neighboring bit states. The high-resistance-state (HRS) and low-resistance-state (LRS) current populations remain clearly separated, with a worst-case LRS/HRS ratio of 140.94×. Robust voltage-domain sensing, multi-row disturb, independent RESET, process, voltage, and temperature (PVT) variation and Monte Carlo characterization, and complete-system area, energy, and latency evaluation remain outside the completed scope.