A Fully Monolithic 2.5 GHz LC Voltage Controlled Oscillator in 0.35 μm CMOS Technology

Abstract

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors.

This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed.