Enabling Development of OpenCL Applications on FPGA platforms

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dc.contributor.authorShagrithaya, Kavya Subrayaen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberSchaumont, Patrick R.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:43:52Zen
dc.date.adate2012-09-17en
dc.date.available2014-03-14T20:43:52Zen
dc.date.issued2012-08-06en
dc.date.rdate2012-09-17en
dc.date.sdate2012-08-20en
dc.description.abstractFPGAs can potentially deliver tremendous acceleration in high-performance server and embedded computing applications. Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered. At the same time, a significant challenge encountered in their wide-spread acceptance is the laborious efforts required in programming these devices. The increased development time, level of experience needed by the developers, lower turns per day and difficulty involved in faster iterations over designs affect the time-to-market for many solutions. High-level synthesis aims towards increasing the productivity of FPGAs and bringing them within the reach software developers and domain experts. OpenCL is a specification introduced for parallel programming purposes across platforms. Applications written in OpenCL consist of two parts - a host program for initialization and management, and kernels that define the compute intensive tasks. In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to obtain the design specification for compute cores. An architecture provided integrates the cores with memory and host interfaces. The host program in the application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-08202012-095025en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08202012-095025/en
dc.identifier.urihttp://hdl.handle.net/10919/34669en
dc.publisherVirginia Techen
dc.relation.haspartShagrithaya_KS_T_2012.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectField programmable gate arraysen
dc.subjectAutoESLen
dc.subjectOpenCLen
dc.subjectConveyen
dc.subjectHPCen
dc.titleEnabling Development of OpenCL Applications on FPGA platformsen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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