Circuits and Modulation Schemes to Achieve High Power-Density in SiC Grid-connected Converters

The emergence of silicon-carbide (SiC) devices has been a 'game changer' in the field of power electronics. With desirable material properties such as low-loss characteristics, high blocking voltage, and high junction temperature operation, they are expected to drastically increase the power density of power electronics systems. Recent state-of-the-art designs show the power density over 17 ; however, certain factors limit the power density to increase beyond this limit. In this dissertation, three key factors are selected to increase the power density of SiC-based grid-connected three-phase converters. Throughout this dissertation, the techniques and strategies to increase the power density of SiC three-phase converters were investigated.

Firstly, a magnetic integration method was introduced for the coupled inductors in the interleaved three-phase converters. Due to limited current-capacity compared to the silicon insulated-gate bipolar transistors (Si-IGBTs), discrete SiC devices or SiC modules, operate in parallel to handle a large current. When three-phase inverters are paralleled, interleaving can be used, and coupled inductors are employed to limit the circulating current. In Chapter 2, the conventional integration method was extended to integrate three coupled inductors into two; one for differential-mode circulating current and the other for common-mode circulating current. By comparing with prior research work, a 20% reduction in size and weight is demonstrated.

From Chapter 3 to Chapter 5, a full-SiC uninterruptible power supply (UPS) was investigated. With the high switching frequency and fast switching dynamics of SiC devices, strategies on electromagnetic inference become more important, compared to Si-IGBT based inverters. Chapter 3 focuses on a common-mode equivalent circuit model for a topology and pulse width modulation (PWM) scheme selection, to set a noise mitigation strategy in the design phase. A three terminal common-mode electromagnetic interference (EMI) model is proposed, which predicts the impact of the dc-dc stage and a large battery-rack on the output CM noise. Based on the model, severe deterioration of noise by the dc-dc stage and battery-rack can be predicted. Special attention was paid on the selection of the dc-dc stage's topology and the PWM scheme to minimize the impact. With the mitigation strategy, a maximum 16 dB reduction on CM EMI can be achieved for a wide frequency range.

In Chapter 4, an active PWM scheme for a full-SiC three-level back-to-back converter was proposed. The PWM scheme targets the size reduction of two key components: dc-link capacitors and a common-mode EMI filter. The increase in switching frequency calls for a large common-mode EMI filter, and dc-link capacitors in the three-level topology may take a considerable portion in the total volume. To reduce the common-mode noise emission, different combinations of the voltage vectors are investigated to generate center-aligned single pulse common-mode voltage. By such an alignment of common-mode voltage with different vector combinations, noise cancellation between the rectifier and the inverter can be maximally utilized, while the balancing of neutral point voltage can be achieved by the transition between the combinations. Also, to reduce the size of the dc-link capacitor for the three-level back-to-back converter, a compensation algorithm for neutral point voltage unbalance was developed for both differential-mode voltage and the common-mode voltage of the ac-ac stage. The experimental results show a 4 dB reduction on CM EMI, which leads to a 30% reduction on the required CM inductance value. When a 10% variation of neutral point voltage can be handled, the dc-link capacitance can be reduced by 56%.

In Chapter 5, a 20 kW full-SiC UPS prototype was built to demonstrate a possible size-reduction with the proposed PWM scheme, as well as a selection of topologies and PWM schemes based on the model. The power density and efficiency are compared with the state-of-the-art Si-IGBT based UPSs.

Chapter 6 seeks to improve power density by a change in a modulation method. Triangular conduction mode (TCM) operation of the three-level full-SiC inverter was investigated. The switching loss of SiC devices is reported to be concentrated on the turn-on instant. With zero-voltage turn-on of all switches, the switching frequency of a three-level three-phase SiC inverter can be drastically increased, compared to the hard-switching operation. This contributes to the size-reduction of the filter inductors and EMI filters. Based on the design to achieve a 99% peak efficiency, a comparison was made with a full-SiC three-level inverter, operating in continuous conduction mode (CCM), to verify the benefit of the soft switching scheme on the power density. A design procedure for an LCL filter of paralleled TCM inverters was developed. With 3.5 times high switching frequency, the total weight of the filter stage of the TCM inverter can be reduced by 15%, compared to that of the CCM inverter.

Throughout this dissertation, techniques for size reduction of key components are introduced, including coupled inductors in parallel inverters, an EMI filter, dc-link capacitors, and the main boost inductor. From Chapter 2 to 5, the physical size or required value of these key components could be reduced by 20% to 56% by different schemes such as magnetic integration, EMI mitigation strategy through modeling, and an active PWM scheme. An optimization result for a full-SiC UPS showed a 40% decrease in the total volume, compared to the state-of-the-art Si-IGBT solution. Soft-switching modulation for SiC-based three-phase inverters can bring a significant increase in the switching frequency and has the potential to enhance power-density notably. A three-level three-phase full-SiC 40 kW PV inverter with TCM operation contributed to a 15% reduction on the filter weight.