Gate Driver Design and Device Characterization for 3.3 kV SiC MOSFET Modules
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Date
2023-11-02
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Volume Title
Publisher
IEEE
Abstract
A compact and 25-kV isolated gate driver with various protective features has been implemented for 3.3-kV SiC power modules. The gate driver design procedure for circuit production is described in detail. With the implemented gate driver, double pulse test (DPT) is performed to evaluate the switching energy losses and parasitic loop inductance at different voltage conditions. Additionally, the DPT together with Ansys Software are used to characterize the stray inductances.