Integration of VHDL simulation and test verification into a Process Model Graph design environment

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dc.contributor.authorDailey, David M.en
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:50:40Zen
dc.date.adate2009-11-24en
dc.date.available2014-03-14T21:50:40Zen
dc.date.issued1994-06-05en
dc.date.rdate2009-11-24en
dc.date.sdate2009-11-24en
dc.description.abstractThis thesis discusses the ability to maintain a consistent design, simulation, and test verification environment by use of the Process Model Graph (PMG) throughout the development process. This ability extends the functionality of the PMG to include the visualization of simulation results and the verification of test paths within the simulation. These ideas have been implemented within a development tool called the Modeler's Assistant. The integration of the test generation environment into the tool is discussed. The design methodology used in creating the simulation environment is also discussed. Other enhancements to increase the abilities of the tool and improve its usefulness to behavioral test generation and verification are also discussed. Many examples of the new extentions to the tool are presented.en
dc.description.degreeMaster of Scienceen
dc.format.extentx, 150 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-11242009-020247en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11242009-020247/en
dc.identifier.urihttp://hdl.handle.net/10919/46017en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1994.D355.pdfen
dc.relation.isformatofOCLC# 31059192en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1994.D355en
dc.subject.lcshVHDL (Computer hardware description language) -- Computer simulationen
dc.subject.lcshVHDL (Computer hardware description language) -- Testingen
dc.titleIntegration of VHDL simulation and test verification into a Process Model Graph design environmenten
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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