Design of a hardware interface for a high-speed parallel network

dc.contributor.authorHarper, Scott Jefferyen
dc.contributor.committeechairMidkiff, Scott F.en
dc.contributor.committeememberJacobs, Iraen
dc.contributor.committeememberDavis, Nathaniel J. IVen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:26:55Zen
dc.date.adate2009-01-10en
dc.date.available2014-03-14T21:26:55Zen
dc.date.issued1994-08-15en
dc.date.rdate2009-01-10en
dc.date.sdate2009-01-10en
dc.description.abstractParallelism can use existing technology in computer communications network design to provide higher data rates and a greater degree of flexibility than monolithic systems. This research investigates the design of a high-speed Parallel Local Area Network (PLAN) interface. It defines the goals of a PLAN interface as low data latency, high data throughput, scalability, and low cost. Three fundamental PLAN interface categories are proposed to meet these goals. These categories are single-bus, dual-bus, and bus-free adaptors. The relative merits of each category are discussed in terms of suitability to several adaptor applications. Each category is further explored by developing a VHDL model of a representative system. The latency, throughput, and component utilization of each model is measured. For medium to large data sets, the dual-bus design provides slightly greater throughput when transmitting encoded data. When transmitting medium to large unencoded data sets, the bus-free design yields marginally higher throughput. In nearly all cases the bus-free design has a greater latency than either of the bus-based design options. Other insights gained from the models regarding physical construction of each adaptor type are also presented.en
dc.description.degreeMaster of Scienceen
dc.format.extentxi, 145 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-01102009-063929en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-01102009-063929/en
dc.identifier.urihttp://hdl.handle.net/10919/40585en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1994.H377.pdfen
dc.relation.isformatofOCLC# 31459273en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1994.H377en
dc.subject.lcshComputer interfaces -- Designen
dc.subject.lcshLocal area networks (Computer networks) -- Designen
dc.subject.lcshParallel processing (Electronic computers)en
dc.titleDesign of a hardware interface for a high-speed parallel networken
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen
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