A Smart Implementation of Turbo Decoding for Improved Power Efficiency

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dc.contributor.authorJemibewon, Abayomi Oluwaseyien
dc.contributor.committeechairWoerner, Brain D.en
dc.contributor.committeememberDavis, William A.en
dc.contributor.committeememberReed, Jeffrey H.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:41:40Zen
dc.date.adate2000-07-20en
dc.date.available2014-03-14T20:41:40Zen
dc.date.issued2000-07-07en
dc.date.rdate2001-07-20en
dc.date.sdate2000-07-20en
dc.description.abstractError correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge. In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-07202000-11180005en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07202000-11180005/en
dc.identifier.urihttp://hdl.handle.net/10919/34072en
dc.publisherVirginia Techen
dc.relation.haspartthesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectVariable resolutionen
dc.subjectAnalog-to-digital converteren
dc.subjectTurbo Codesen
dc.titleA Smart Implementation of Turbo Decoding for Improved Power Efficiencyen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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