Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform

dc.contributor.authorMarballie, Gladstone Washingtonen
dc.contributor.committeechairBostian, Charles W.en
dc.contributor.committeememberPatterson, Cameron D.en
dc.contributor.committeememberPratt, Timothy J.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.abstractThe Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish physical layer communications using the received signal's profile. The current implementation is able to identify signals including AM, FM, MPSK, QAM, MFSK, and OFDM. The system is constructed to run on a Universal Software Radio Peripheral (USRP) with the GNU Radio software toolkit and also runs on an Anritsu™ signal analyzer. In both prototypes, the UCS system runs on a host computer's General Purpose Processor (GPP) and is constructed in Matlab™. The aim is to then create a portable and standalone version of the UCS system as an intermediate step towards building a future commercial implementation. This application and particular implementation aims to run on a Lyrtech SFF SDR platform and uses its FPGA and DSP modules for implementation. This platform is one of the more advanced SDR platforms available, and the aim is to develop parts of the UCS system to run on this platform. The aim is to eventually develop the complete UCS cognitive radio system on the Lyrtech SFF SDR platform that can act as a standalone portable cognitive radio system. The modules created and implanted/implemented on the SDR hardware are the Bandwidth Estimation, and Symbol Timing & Coarse Classification modules. This is the system decision path towards classification, synchronization, and demodulation of digital phase modulated signals (QAM and MPSK signal types) and also analog signals. The Digital Receiver Module (DRM) is implemented on the FPGA and takes care of all the digital down conversions, mixing, decimation, and low pass filtering. The FPGA is connected to the DSP module via a bus subsystem where the DSP receives real-time base-band complex IQ samples for further signal processing. The main UCS algorithm runs on the platform's DSP and is compiled from executable embedded C-code. Therefore, this system can then be implemented on virtually any setup that has an RF front end, digital receiver module, and processing module that will execute floating and fixed point C-code with minor changes.en
dc.description.degreeMaster of Scienceen
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.subjectField programmable gate arraysen
dc.subjectSignal Classificationen
dc.subjectSymbol Timingen
dc.subjectCognitive radio networksen
dc.titleSymbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platformen
dc.typeThesisen and Computer Engineeringen Polytechnic Institute and State Universityen of Scienceen
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