Image Chipping with a Common Architecture for Microsensors (CAuS)

dc.contributor.authorScalera, Jonathan E.en
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.committeememberBell, Amy E.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:41:59Zen
dc.date.adate2001-08-16en
dc.date.available2014-03-14T20:41:59Zen
dc.date.issued2001-07-23en
dc.date.rdate2002-08-16en
dc.date.sdate2001-07-26en
dc.description.abstractRecent interest has emerged in microsensor platforms that are capable of supporting reconnaissance, surveillance and target acquisition operations. These devices typically consist of one or more sensors, signal conditioning and processing subsystems, a radio link and a power source. Sensors employed can range from acoustic, to seismic, to magnetic, to visible/infrared imagers. A notable shortcoming of these systems is the fact that they are battery powered. The use of a finite power source places an upper limit on the lifespan of such a system. Thus, a major thrust in the development and usage of these microsensor platforms lies in the conservation of their limited energy resources. In attempt to reduce power consumption and hence extend the system's lifespan, communication bandwidths are often limited. In order to reduce the required bandwidth, much of the signal processing necessary to achieve a desired functionality must be performed within the microsensor platform itself. This thesis effort provides this crucial bandwidth reduction by implementing in hardware an algorithm developed by the University of Maryland, which limits transmissions to the best view Regions-of-Interest (ROI) data, on the CAuS platform by BAE Systems. The hardware implementation was verified with a Matlab script that compared its results with those of the original algorithm. It was shown that these implementations were consistent for all of the data sets tested. Moreover, a subjective analysis, in which the detected ROIs were visually inspected, was performed to corroborate the former quantitative results.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-07262001-041111en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07262001-041111/en
dc.identifier.urihttp://hdl.handle.net/10919/34172en
dc.publisherVirginia Techen
dc.relation.haspartthesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectMicrosensorsen
dc.subjectCAuSen
dc.subjectImage Processingen
dc.subjectField programmable gate arraysen
dc.subjectRegion of Interest (ROI)en
dc.titleImage Chipping with a Common Architecture for Microsensors (CAuS)en
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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