Coarse Radio Signal Classifier on a Hybrid FPGA/DSP/GPP Platform

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dc.contributor.authorNair, Sujit S.en
dc.contributor.committeechairBostian, Charles W.en
dc.contributor.committeememberMacKenzie, Allen B.en
dc.contributor.committeememberPatterson, Cameron D.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2017-04-04T19:50:24Zen
dc.date.adate2010-01-12en
dc.date.available2017-04-04T19:50:24Zen
dc.date.issued2009-12-07en
dc.date.rdate2016-10-07en
dc.date.sdate2009-12-21en
dc.description.abstractThe Virginia Tech Universal Classifier Synchronizer (UCS) system can enable a cognitive receiver to detect, classify and extract all the parameters needed from a received signal for physical layer demodulation and configure a cognitive radio accordingly. Currently, UCS can process analog amplitude modulation (AM) and frequency modulation (FM) and digital narrow band M-PSK, M-QAM and wideband signal orthogonal frequency division multiplexing (OFDM). A fully developed prototype of UCS system was designed and implemented in our laboratory using GNU radio software platform and Universal Software Radio Peripheral (USRP) radio platform. That system introduces a lot of latency issues because of the limited USB data transfer speeds between the USRP and the host computer. Also, there are inherent latencies and timing uncertainties in the General Purpose Processor (GPP) software itself. Solving the timing and latency problems requires running key parts of the software-defined radio (SDR) code on a Field Programmable Gate Array (FPGA)/Digital Signal Processor (DSP)/GPP based hybrid platform. Our objective is to port the entire UCS system on the Lyrtech SFF SDR platform which is a hybrid DSP/FPGA/GPP platform. Since the FPGA allows parallel processing on a wideband signal, its computing speed is substantially faster than GPPs and most DSPs, which sequentially process signals. In addition, the Lyrtech Small Form Factor (SFF)-SDR development platform integrates the FPGA and the RF module on one platform; this further reduces the latency in moving signals from RF front end to the computing component. Also for UCS to be commercially viable, we need to port it to a more portable platform which can be transitioned to a handset radio in the future. This thesis is a proof of concept implementation of the coarse classifier which is the first step of classification. Both fixed point and floating point implementations are developed and no compiler specific libraries or vendor specific libraries are used. This makes transitioning the design to any other hardware like GPPs and DSPs of other vendors possible without having to change the basic framework and design.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-12212009-235313en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12212009-235313/en
dc.identifier.urihttp://hdl.handle.net/10919/76934en
dc.language.isoen_USen
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSDRen
dc.subjectField programmable gate arraysen
dc.subjectDSPen
dc.subjectGPPen
dc.subjectSignal Classifieren
dc.subjectCognitive radio networksen
dc.titleCoarse Radio Signal Classifier on a Hybrid FPGA/DSP/GPP Platformen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen
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