On-Chip Isotropic Microchannels for Cooling Three Dimensional Microprocessors

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Virginia Tech

This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C.

To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer.

Chip Cooling, 3D IC, MEMS, CMOS Compatible, Microfluidics, Buried Channel