Modeling and Synthesis with SystemC

dc.contributor.authorVarma, Anupen
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.committeememberBaker, James M. Jr.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:50:09Zen
dc.date.adate2002-01-03en
dc.date.available2014-03-14T20:50:09Zen
dc.date.issued2001-12-13en
dc.date.rdate2003-01-03en
dc.date.sdate2001-12-17en
dc.description.abstractWith the increasing complexity of Application Specific Integrated Circuits (ASICs), System-On-a-Chip (SoC) design seems to be the current chip design paradigm. Unlike ASICs, SoCs are a potpourri of diverse components, including general-purpose or special-purpose processors. Designing and testing these designs require a new methodology that supports system level modeling and hardware-software co-design. The Hardware Description Languages (HDLs) available today cannot meet this challenge. SystemC is a new modeling language based on C++. Models written in SystemC are executable and do not dictate either hardware or software implementation. The model written in SystemC can be synthesized to hardware using the CoCentric SystemC Compiler (CCSC). Thus, the combination of SystemC and CCSC has the potential to be a powerful SoC design technique. This thesis examines the usefulness of SystemC and CCSC to model and synthesize a GSM system. The encoders and decoders used in the GSM system are complex and represent challenging problems in the real world. The modeling methodology using SystemC is considered and the synthesis issues with CCSC are detailed. Simulation results using real sound samples and synthesis results are presented. Areas for future work are then outlined.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-12172001-152439en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12172001-152439/en
dc.identifier.urihttp://hdl.handle.net/10919/36222en
dc.publisherVirginia Techen
dc.relation.haspartThesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectsynthesisen
dc.subjectModelingen
dc.subjectGSMen
dc.subjectCoCentricen
dc.subjectSystemCen
dc.titleModeling and Synthesis with SystemCen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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