Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs
This dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. Different from other incremental placement algorithms, this tool provides the function not only to handle small modifications; it can also incrementally place a large design from scratch at a rapid rate. Incremental approaches are inherently greedy techniques, but when combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An incremental FPGA design tool has been developed, based on the incremental placement algorithm and its background refiner.
Design applications with logical gate sizes varying from tens of thousands to approximately one million are built to evaluate the execution of the algorithms and the design tool. The results show that this incremental design tool is two orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing much quality. The tool presented places designs at the speed of 700,000 system gates per second. The fast processing speed and user-interactive property make the incremental design tool potentially useful for prototype developing, system debugging and modular testing in million-gate FPGA designs.