dc.contributor.author	Ma, Jing	en
dc.contributor.committeecochair	Jones, Mark T.	en
dc.contributor.committeecochair	Athanas, Peter M.	en
dc.contributor.committeemember	Varadarajan, Srinidhi	en
dc.contributor.committeemember	Woerner, Brain D.	en
dc.contributor.committeemember	Midkiff, Scott F.	en
dc.contributor.department	Electrical and Computer Engineering	en
dc.date.accessioned	2014-03-14T20:06:48Z	en
dc.date.adate	2003-01-22	en
dc.date.available	2014-03-14T20:06:48Z	en
dc.date.issued	2003-01-13	en
dc.date.rdate	2004-01-22	en
dc.date.sdate	2003-01-20	en
dc.description.abstract	This dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. Different from other incremental placement algorithms, this tool provides the function not only to handle small modifications; it can also incrementally place a large design from scratch at a rapid rate. Incremental approaches are inherently greedy techniques, but when combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An incremental FPGA design tool has been developed, based on the incremental placement algorithm and its background refiner. Design applications with logical gate sizes varying from tens of thousands to approximately one million are built to evaluate the execution of the algorithms and the design tool. The results show that this incremental design tool is two orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing much quality. The tool presented places designs at the speed of 700,000 system gates per second. The fast processing speed and user-interactive property make the incremental design tool potentially useful for prototype developing, system debugging and modular testing in million-gate FPGA designs.	en
dc.description.degree	Ph. D.	en
dc.identifier.other	etd-01202003-151943	en
dc.identifier.sourceurl	http://scholar.lib.vt.edu/theses/available/etd-01202003-151943/	en
dc.identifier.uri	http://hdl.handle.net/10919/26016	en
dc.publisher	Virginia Tech	en
dc.relation.haspart	Chapter6.pdf	en
dc.relation.haspart	Tableofcontents.pdf	en
dc.relation.haspart	Chapter7.pdf	en
dc.relation.haspart	Chapte1&2.pdf	en
dc.relation.haspart	Chapter5.pdf	en
dc.relation.haspart	Chapter4.pdf	en
dc.relation.haspart	Bibliography.pdf	en
dc.relation.haspart	Chapter8.pdf	en
dc.relation.haspart	Chapter3.pdf	en
dc.rights	In Copyright	en
dc.rights.uri	http://rightsstatements.org/vocab/InC/1.0/	en
dc.subject	Incremental Design	en
dc.subject	Design Tool	en
dc.subject	Field programmable gate arrays	en
dc.subject	Placement	en
dc.title	Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs	en
dc.type	Dissertation	en
thesis.degree.discipline	Electrical and Computer Engineering	en
thesis.degree.grantor	Virginia Polytechnic Institute and State University	en
thesis.degree.level	doctoral	en
thesis.degree.name	Ph. D.	en

Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs

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