VTechWorks staff will be away for the winter holidays starting Tuesday, December 24, 2024, through Wednesday, January 1, 2025, and will not be replying to requests during this time. Thank you for your patience, and happy holidays!
 

Representation and simulation of a high level language using VHDL

Simple item page
dc.contributor.authorEdwards, Carleen Marieen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.committeememberKeenan, Michael A.en
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:50:43Zen
dc.date.adate2009-11-24en
dc.date.available2014-03-14T21:50:43Zen
dc.date.issued1994-12-05en
dc.date.rdate2009-11-24en
dc.date.sdate2009-11-24en
dc.description.abstractThis paper presents an approach for representing and simulating High Level Languages (HLL) using VHDL behavioral models. The graphical representation, a Data Flow Graph (DFG), is used as a base for the VHDL representation and simulation of a High Level Language (C). A package of behavioral models for the functional units for the High Level Language as well as individual entities has been developed using VHDL. An algorithm, Graph2VHDL, accepts a Data Flow Graph representation of a High Level Language and constructs a VHDL model for that graph. The representation of a High Level Language in VHDL frees users of custom computing platforms from the tedious job of developing a hardware model for a desired application. The algorithm also constructs a test file that is used with a pre-existing program, Test Bench Generation (TBG), to create a test-bench for the VHDL model of a Data Flow Graph. The test bench that is generated is used to simulate the representation of the High Level Language in the Data Flow Graph format. Experimental results verify the representation of the High Level Language in the Data Flow Graph format and in VHDL is correct.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 67 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-11242009-020306en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11242009-020306/en
dc.identifier.urihttp://hdl.handle.net/10919/46021en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1994.E3925.pdfen
dc.relation.isformatofOCLC# 32228141en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1994.E3925en
dc.subject.lcshProgramming languages (Electronic computers)en
dc.subject.lcshVHDL (Computer hardware description language)en
dc.titleRepresentation and simulation of a high level language using VHDLen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
LD5655.V855_1994.E3925.pdf
Size:
1.77 MB
Format:
Adobe Portable Document Format
Download

Collections

Masters Theses