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Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures

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dc.contributor.authorBhaduri, Debayanen
dc.contributor.committeechairShukla, Sandeep K.en
dc.contributor.committeememberRavindran, Binoyen
dc.contributor.committeememberHa, Dong Samen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2011-08-06T16:01:31Zen
dc.date.adate2004-05-20en
dc.date.available2011-08-06T16:01:31Zen
dc.date.issued2002-12-02en
dc.date.rdate2004-05-20en
dc.date.sdate2004-05-12en
dc.description.abstractIt is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates, and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause degradation in reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome, and do not scalewell for complex networks of gates. In this thesiswe develop different tools and techniques that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is named NANOPRISM, and another MATLAB based tool called NANOLAB. We also illustrate the effectiveness of our reliability analysis tools by pointing out certain anomalies which are counter-intuitive but can be easily discovered by these tools, thereby providing better insight into defecttolerant design decisions. We believe that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-05122004-121332en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-05122004-121332en
dc.identifier.urihttp://hdl.handle.net/10919/9918en
dc.publisherVirginia Techen
dc.relation.haspartbhaduri_debayan_thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectdefect-tolerant architectureen
dc.subjectGaussianen
dc.subjectreliabilityen
dc.subjectPRISMen
dc.subjectgranularityen
dc.subjectCTMRen
dc.subjectentropyen
dc.subjectprobabilistic model checkingen
dc.subjectinterconnect noiseen
dc.subjectModelingen
dc.subjectTMRen
dc.subjectGibbs distributionen
dc.subjectNanotechnologyen
dc.titleTools and Techniques for Evaluating Reliability Trade-offs for Nano-Architecturesen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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