Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration

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dc.contributor.authorBlumer, Aric Daviden
dc.contributor.committeechairPatterson, Cameron D.en
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.committeememberBroadwater, Robert P.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.committeememberMortveit, Henning S.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:17:42Zen
dc.date.adate2007-11-16en
dc.date.available2014-03-14T20:17:42Zen
dc.date.issued2007-10-15en
dc.date.rdate2007-11-16en
dc.date.sdate2007-10-26en
dc.description.abstractThe run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms.en
dc.description.degreePh. D.en
dc.identifier.otheretd-10262007-144416en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-10262007-144416/en
dc.identifier.urihttp://hdl.handle.net/10919/29380en
dc.publisherVirginia Techen
dc.relation.haspartetd2.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectRTL Simulationen
dc.subjectProcess Migrationen
dc.subjectRun-time Reconfigurationen
dc.subjectReconfigurable Computingen
dc.subjectFormal Modelingen
dc.subjectCanonical RTLen
dc.subjectExecutive Locality of Referenceen
dc.titleRegister Transfer Level Simulation Acceleration via Hardware/Software Process Migrationen
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en

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