Sequential logic design using counters as memory elements
| dc.contributor.author | Schrank, Arthur David | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2016-02-01T18:05:43Z | en |
| dc.date.available | 2016-02-01T18:05:43Z | en |
| dc.date.issued | 1974 | en |
| dc.description.abstract | This thesis is concerned with the use of memory function devices in place of binary storage devices in sequential machines. In particular, various counters are considered as memory elements. Design limitations and design procedures for each type of counter are determined, with emphasis placed on UP/DN/PRESET type counters. It is shown that a presettable counter is capable of realizing any sequential machine. Special considerations involved in state assignment and minimization in designs using counters are investigated. Finally, extensions and areas of possible further study are discussed. | en |
| dc.description.degree | Master of Science | en |
| dc.format.extent | 45 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/64704 | en |
| dc.language.iso | en_US | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 21651719 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1974.S35 | en |
| dc.subject.lcsh | Logic design | en |
| dc.subject.lcsh | Memory | en |
| dc.title | Sequential logic design using counters as memory elements | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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