Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

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dc.contributor.authorIskander, Yousef Shafiken
dc.contributor.committeechairPatterson, Cameron D.en
dc.contributor.committeememberPlassmann, Paul D.en
dc.contributor.committeememberRiad, Sedki Mohameden
dc.contributor.committeememberBurdisso, Ricardo A.en
dc.contributor.committeememberMartin, Thomas L.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:15:24Zen
dc.date.adate2012-09-11en
dc.date.available2014-03-14T20:15:24Zen
dc.date.issued2012-08-06en
dc.date.rdate2012-11-13en
dc.date.sdate2012-08-18en
dc.description.abstractDesign validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.en
dc.description.degreePh. D.en
dc.identifier.otheretd-08182012-001148en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08182012-001148/en
dc.identifier.urihttp://hdl.handle.net/10919/28716en
dc.publisherVirginia Techen
dc.relation.haspartIskander_YS_D_2012.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectpartial reconfigurationen
dc.subjectreconfigurable computingen
dc.subjectField programmable gate arraysen
dc.subjectdevelopmenten
dc.subjectdebugen
dc.subjectdesign validationen
dc.titleImproved Abstractions and Turnaround Time for FPGA Design Validation and Debugen
dc.typeDissertationen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.leveldoctoralen
thesis.degree.namePh. D.en
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