Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity

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dc.contributor.authorChandrasekharan, Athiraen
dc.contributor.committeechairPatterson, Cameron D.en
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.committeememberPlassmann, Paul E.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:43:21Zen
dc.date.adate2010-08-17en
dc.date.available2014-03-14T20:43:21Zen
dc.date.issued2010-08-05en
dc.date.rdate2012-06-22en
dc.date.sdate2010-08-12en
dc.description.abstractFPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-08122010-161305en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08122010-161305/en
dc.identifier.urihttp://hdl.handle.net/10919/34499en
dc.publisherVirginia Techen
dc.relation.haspartChandrasekharan_A_T_2010.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectReconfigurable Computingen
dc.subjectIncremental Floorplanningen
dc.subjectFPGAsen
dc.titleAccelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivityen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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