Fault simulation for supply current testing of bridging faults in CMOS circuits

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Virginia Tech


The objective of this research is to develop and implement a method for fault simulation that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level hierarchy. At the higher level, the circuit is partitioned into modules based on the circuit layout. Each module is represented at the lower level by a switch-level graph. This representation has the advantage of structural accuracy at the lower level and efficient logic propagation at the higher level. Based on a module's switch-level graph, an exhaustive list of bridging faults corresponding to certain physical defects can be derived. Fault collapsing techniques are used to optimize the exhaustive fault list. There are two major processes in this bridging fault simulation program, logic simulation and fault sensitization at switch level. The simulation program uses preprocessing and bit-wise parallelism to minimize computation time. At the end of fault simulation, a fault coverage and fault matrices suitable for test grading and fault diagnosis are produced for each test set.

This research also identifies types of CMOS modules and uses them to analyze test generation for bridging faults. The completeness and minimality of switch-level test sets are considered for general series-parallel (GSP) modules. Finally, several single-module circuits are simulated using gate-level, switch-level and random test sets, and their effectiveness is compared.