A fault tolerant bus interface unit based on the nubus standardized bus architecture

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Virginia Polytechnic Institute and State University


Microprocessor-based systems are used for a variety of applications, ranging from industrial control systems to spaceborne systems. The complex nature of tasks to be performed has led to division and distribution of work among different subsystems. A fast and reliable means of information and data transmission among these subsystems is provided by parallel communication busses.

Satellite-based systems are susceptible to transient faults caused by cosmic radiation or alpha particles. In order for a system to be usable in such an environment, it must be designed to be upset tolerant. Functionality of the design must be intact in the presence of transient faults.

Several standardized bus architectures have been configured to meet a given set of performance specifications. One such bus architecture called the Nubus is used as the basis for the design and development of an upset tolerant bus architecture. The modified structure is called NuFTbus for Nu Fault-Tolerant bus. Rationale for the NuFTbus specification is presented in this thesis. A design of an IC-based bus interface unit is developed. The design is specified in the VHSIC Hardware Description Language (VHDL) and VHDL tools are used to simulate the system behavior. Simulation results are presented. The VHDL circuit description is converted to a gate array layout ready For Fabrication in an appropriate radiation-hardened gate array technology. A description oF the hardware Functional testing Facilities, along with a description of a set of test procedures, is given.