Optimal constructs for chip level modeling

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dc.contributor.authorHan, Dongilen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2019-10-10T19:11:50Zen
dc.date.available2019-10-10T19:11:50Zen
dc.date.issued1986en
dc.description.abstractAnalysis and comparison of nine different Hardware Description Languages is presented. Comparison features are discussed and each language is analysed according to the comparison features, which are: sequencing mechanisms, applicability to generic structures, abstraction of data and operation, timing mode, communication mechanisms, and instantiation and interconnection of elements. Based on the analysis of the languages, optimal constructs for chip level modeling are extracted. Example descriptions of a microprocessor system MARK 2 are presented.en
dc.description.degreeM.S.en
dc.format.extentviii, 154 leavesen
dc.format.mimetypeapplication/pdfen
dc.identifier.urihttp://hdl.handle.net/10919/94469en
dc.language.isoen_USen
dc.publisherVirginia Polytechnic Institute and State Universityen
dc.relation.isformatofOCLC# 15254991en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1986.H3663en
dc.subject.lcshDigital electronicsen
dc.titleOptimal constructs for chip level modelingen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameM.S.en

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