Design and Implementation of an FPGA-based Adaptive filter Single-User Receiver

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dc.contributor.authorAtiniramit, Prinyaen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberReed, Jeffrey H.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:46:38Zen
dc.date.adate1999-10-13en
dc.date.available2014-03-14T20:46:38Zen
dc.date.issued1999-09-17en
dc.date.rdate2000-10-13en
dc.date.sdate1999-10-12en
dc.description.abstractDuring the last decade, the wireless communications industry has grown rapidly. Driven by market demand, service providers are continuously looking for better systems. The main focus of continued research has been to increase the quality of services and system capacity. The Code Division Multiple Access (CDMA) cellular system had been proposed for use as a new standard for cellular telephone systems. A great deal of research has been conducted to develop receiver structures useful for CDMA systems. Traditional receivers such as the correlation and RAKE receivers are vulnerable to the near-far problem, i.e., the problem encountered when one received signal power is stronger than another. This problem is common in mobile environments. For single-user receivers, adaptive filtering techniques can be employed to alleviate multiple access interference and the near-far problem. In this thesis, an adaptive filter receiver is implemented on the FPGA-based configurable computing platform called GigaOps G900. By using FPGAs, designers can implement special-purpose signal processing architectures using specialized data paths, optimized sequencing, and pipelining while still providing some flexibility. This results in better overall system performance, resource utilization, and reduced power consumption.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-101299-012534en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-101299-012534/en
dc.identifier.urihttp://hdl.handle.net/10919/35368en
dc.publisherVirginia Techen
dc.relation.haspartthesis1.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectField programmable gate arraysen
dc.subjectadaptive filter receiveren
dc.subjectCDMAen
dc.subjectCCMen
dc.titleDesign and Implementation of an FPGA-based Adaptive filter Single-User Receiveren
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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