Image Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machine

dc.contributor.authorDing, Zhimeien
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberMidkiff, Scott F.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:41:47Zen
dc.date.adate2000-08-22en
dc.date.available2014-03-14T20:41:47Zen
dc.date.issued2000-06-14en
dc.date.rdate2001-08-22en
dc.date.sdate2000-07-22en
dc.description.abstractThis thesis presents the design and implementation of the Image Wavelet Compression (IWC) algorithm on Field Programmable Gate Arrays (FPGAs) by using the run-time reconfigurable custom computing machine design tool Janus. The four routines implementing the IWC are discussed. The structure of Janus is introduced and the IWC implementation design framework to use Janus structure is described in detail. The Janus hardware circuit design model, which has been used in the IWC implementation, is demonstrated here. The hardware implementation results are presented and analyzed, focusing on reconfiguration and computing time. Future research areas are suggested to improve the Janus tool.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-07222000-13030026en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07222000-13030026/en
dc.identifier.urihttp://hdl.handle.net/10919/34105en
dc.publisherVirginia Techen
dc.relation.haspartThesisPDF84.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGA RTRC CCMen
dc.titleImage Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machineen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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