Tri-state gates in logical networks
dc.contributor.author | Aglietti, Robert B. | en |
dc.contributor.department | Electrical Engineering | en |
dc.date.accessioned | 2016-04-21T15:34:31Z | en |
dc.date.available | 2016-04-21T15:34:31Z | en |
dc.date.issued | 1975 | en |
dc.description.abstract | Several methods were presented to facilitate the use of tri-state gates in the design of logic networks. Special considerations for the use of tri-state gates are discussed in order that the reader might get a feel for the capability of tri-state logic and so that he will be aware of problems which may appear in the course of the design and development of a tri-state logic network. Several problems are worked, both combinational and sequential examples, and the advantages of tri-state over classical logic are discussed. Two additional examples, one of an iterative network and one of a multi-functional cell illustrate the applicability of tri-state gates to many digital designs. | en |
dc.description.degree | Master of Science | en |
dc.format.extent | v, 65 leaves | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.uri | http://hdl.handle.net/10919/70461 | en |
dc.language.iso | en | en |
dc.publisher | Virginia Polytechnic Institute and State University | en |
dc.relation.isformatof | OCLC# 33352253 | en |
dc.rights | In Copyright | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.subject.lcc | LD5655.V855 1975.A36 | en |
dc.title | Tri-state gates in logical networks | en |
dc.type | Thesis | en |
dc.type.dcmitype | Text | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | masters | en |
thesis.degree.name | Master of Science | en |
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