A distributed control reconfiguration algorithm for 2-dimensional mesh architectures which tolerates single faults per row
dc.contributor.author | White, Tennis S. | en |
dc.contributor.committeechair | Gray, Festus Gail | en |
dc.contributor.committeemember | Tront, Joseph G. | en |
dc.contributor.committeemember | McKeeman, John C. | en |
dc.contributor.department | Electrical Engineering | en |
dc.date.accessioned | 2014-03-14T21:50:25Z | en |
dc.date.adate | 2012-11-21 | en |
dc.date.available | 2014-03-14T21:50:25Z | en |
dc.date.issued | 1988-05-05 | en |
dc.date.rdate | 2012-11-21 | en |
dc.date.sdate | 2012-11-21 | en |
dc.description.abstract | A reconfiguration is developed for 2-dimensional mesh architectures and applied to a fault T tolerant cellular architecture. The reconfiguration is accomplished by adding communications paths to each cell which can be enabled by means of transistor switches controlled by decoding the contents of a register containing the relative position of faulty cells. This enables faulty cells to be bypassed and operations of cells in the same row east of the faulty cell to be shifted one cell to the east and a spare cell included in the active pattern. A modified s-value algorithm is also developed which enables a cell to determine the size of a square pattern that may be centered on that cell. | en |
dc.description.degree | Master of Science | en |
dc.format.extent | vii, 133 leaves | en |
dc.format.medium | BTD | en |
dc.format.mimetype | application/pdf | en |
dc.identifier.other | etd-11212012-040115 | en |
dc.identifier.sourceurl | http://scholar.lib.vt.edu/theses/available/etd-11212012-040115/ | en |
dc.identifier.uri | http://hdl.handle.net/10919/45945 | en |
dc.language.iso | en | en |
dc.publisher | Virginia Tech | en |
dc.relation.haspart | LD5655.V855_1988.W536.pdf | en |
dc.relation.isformatof | OCLC# 18344594 | en |
dc.rights | In Copyright | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.subject.lcc | LD5655.V855 1988.W536 | en |
dc.subject.lcsh | Array processors | en |
dc.subject.lcsh | Multiprocessors | en |
dc.title | A distributed control reconfiguration algorithm for 2-dimensional mesh architectures which tolerates single faults per row | en |
dc.type | Thesis | en |
dc.type.dcmitype | Text | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | masters | en |
thesis.degree.name | Master of Science | en |
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