Generation of VHDL from conceptual graphs of informal specifications

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dc.contributor.authorHoncharik, Alexander J.en
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberCyre, Walling R.en
dc.contributor.committeememberHa, Dong Samen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:38:31Zen
dc.date.adate2009-06-16en
dc.date.available2014-03-14T21:38:31Zen
dc.date.issued1993-05-05en
dc.date.rdate2009-06-16en
dc.date.sdate2009-06-16en
dc.description.abstractThis thesis describes two ongoing projects at Virginia Tech called ASPIN and the Modeler's Assistant, but is primarily concerned with a computer program known as "The VHDL Linker." This program is an interface between the two systems and interprets conceptual graphs generated from English sentences describing the behavior of a device, and produces a Process Model Graph and the associated VHDL code for use by the Modeler's Assistant. The ASPIN (Automated SPecification INterpreter) system translates English sentences describing the behavior of a device into a data structure known as conceptual graphs. Ultimately block diagrams and timing diagrams will be translated as well. The VHDL Linker translates these conceptual graphs into Process Model Graphs (PMGs) and corresponding VHDL code. Once a PMG (and associated VHDL code) has been created it can be edited as needed on the Modeler's Assistant, to fill in any holes left by the interpreters, correct errors, expand the model, or make it more specific as component designs become available. This research is the first step towards the development of a system which will allow a designer who is unfamiliar with VHDL to create a working VHDL model from informal specifications. Such a system will reduce the time from initial conception to a working design dramatically.en
dc.description.degreeMaster of Scienceen
dc.format.extentvii, 127 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-06162009-063028en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06162009-063028/en
dc.identifier.urihttp://hdl.handle.net/10919/43313en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1993.H662.pdfen
dc.relation.isformatofOCLC# 29040813en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1993.H662en
dc.subject.lcshComputer graphicsen
dc.subject.lcshVHDL (Computer hardware description language)en
dc.titleGeneration of VHDL from conceptual graphs of informal specificationsen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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