Analysis, simulation and modeling of three-level VSIs

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dc.contributor.authorCosan, Muhammeten
dc.contributor.committeechairBoroyevich, Dushanen
dc.contributor.committeememberLee, Fred C.en
dc.contributor.committeememberLai, Jih-Shengen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:43:18Zen
dc.date.adate2008-08-22en
dc.date.available2014-03-14T21:43:18Zen
dc.date.issued1997-11-05en
dc.date.rdate2008-08-22en
dc.date.sdate2008-08-22en
dc.description.abstractAnalysis of three-phase, three-level VSIs is done for high-power high-voltage applications. Complete Space Vector Modulation (SVM) algorithm is developed for a three-phase, three-level converter. Special attention is given to minimization of output ripple and voltage balance of the dc-link input capacitors. Verification of the proposed SVM algorithm is done by computer simulation. Comprehensive small-signal modeling of the three-level converter with a resistive load is developed the first time. Steady-state solutions reveal that the voltage across dc-link input capacitors is constant at the half of the dc-link voltage.en
dc.description.degreeMaster of Scienceen
dc.format.extentviii, 92 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-08222008-063802en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08222008-063802/en
dc.identifier.urihttp://hdl.handle.net/10919/44365en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1997.C673.pdfen
dc.relation.isformatofOCLC# 39849308en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectthree-level converteren
dc.subject.lccLD5655.V855 1997.C673en
dc.titleAnalysis, simulation and modeling of three-level VSIsen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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