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dc.contributor.authorNakad, Zahi Samiren
dc.date.accessioned2014-03-14T20:47:48Zen
dc.date.available2014-03-14T20:47:48Zen
dc.date.issued2000-09-20en
dc.identifier.otheretd-11132000-12050007en
dc.identifier.urihttp://hdl.handle.net/10919/35682en
dc.description.abstractMany problems faced in the engineering world are computationally intensive. Filtering using FIR (Finite Impulse Response) filters is an example to that. This thesis discusses the implementation of a fast, reconfigurable, and scalable FIR (Finite Impulse Response) digital filter. Constant coefficient multipliers and a Fast FIFO implementation are also discussed in connection with the FIR filter. This filter is used in two of its structures: the direct-form and the lattice structure. The thesis describes several configurations that can be created with the different components available and reports the testing results of these configurations.en
dc.publisherVirginia Techen
dc.relation.haspartThesis_Submission.PDFen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFIR filtersen
dc.subjectField programmable gate arraysen
dc.subjectreconfigurable computingen
dc.subjectconstant coefficient multipliersen
dc.titleHigh Performance Applications on Reconfigurable Clustersen
dc.typeThesisen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical and Computer Engineeringen
dc.contributor.committeechairJones, Mark T.en
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.committeememberArmstrong, James R.en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11132000-12050007/en
dc.date.sdate2000-11-13en
dc.date.rdate2001-11-14en
dc.date.adate2000-11-14en


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