Generation of VHDL from conceptual graphs of informal specifications
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The ASPIN (Automated SPecification INterpreter) system translates English sentences describing the behavior of a device into a data structure known as conceptual graphs. Ultimately block diagrams and timing diagrams will be translated as well. The VHDL Linker translates these conceptual graphs into Process Model Graphs (PMGs) and corresponding VHDL code.
Once a PMG (and associated VHDL code) has been created it can be edited as needed on the Modeler's Assistant, to fill in any holes left by the interpreters, correct errors, expand the model, or make it more specific as component designs become available.
This research is the first step towards the development of a system which will allow a designer who is unfamiliar with VHDL to create a working VHDL model from informal specifications. Such a system will reduce the time from initial conception to a working design dramatically.
- Masters Theses