Toggle navigation
Log in
Toggle navigation
View Item
VTechWorks Home
ETDs: Virginia Tech Electronic Theses and Dissertations
Masters Theses
View Item
VTechWorks Home
ETDs: Virginia Tech Electronic Theses and Dissertations
Masters Theses
View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.
An Algorithm for multi-output Boolean logic minimization
View/
Open
LD5655.V855_1987.V672.pdf (4.194Mb)
Downloads: 110
Date
1987
Author
Vora, Rohit H.
Metadata
Show full item record
URI
http://hdl.handle.net/10919/43829
Collections
Masters Theses
[19615]
Search VTechWorks
This Collection
VTechWorks
About
Policies
Help
Browse
All of VTechWorks
Communities & Collections
By Issue Date
Authors
Titles
Subjects
This Collection
By Issue Date
Authors
Titles
Subjects
My Account
Log in
Register
Statistics
View Usage Statistics
