Starting in September 1984, the Telesign project is an extensive and complex project proposed and undertaken by Dr. Nadler at Virginia Tech. The emphasis of this project is to enable the members of the deaf community to communicate visually using sign language or lip reading over the telephone network.

The Image Processing Board (IPB) is the 'Brain' of the whole system. The IPB processes a given frame of an image to transmit only selected data. It uses the pseudo-laplacian operator, invented by Dr. Nadler, for edge detection. According to a recent survey of various edge detection algorithms by D. E. Pearson, [1], the pseudo-laplacian operator is the most efficient one and it produces the most natural pictures.

The whole IPB hosts about one hundred LSI/VLSI chips according to the present hardware description. In the case of such a big system, hardware simulation becomes mandatory in order to ensure reliability of the design and to anticipate any kind of logic or timing errors in the design. This thesis describes the modifications to the original design to make it reconfigurable with proper initialization and the Hardware Simulation of the IPB, using General Simulation Program (GSP), including some comments on the simulators available at Virginia Tech and in particular a critique of the simulator used here. Many improvements to the simulator are suggested. Precautions to be taken while preparing the lay-out and wiring of the IPB, suggestions to simplify the design at some points at the cost of a few more chips, and lastly the instructions to run the models to get the required results, are outlined in this thesis.