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dc.contributor.authorSchrank, Arthur Daviden
dc.date.accessioned2016-02-01T18:05:43Zen
dc.date.available2016-02-01T18:05:43Zen
dc.date.issued1974en
dc.identifier.urihttp://hdl.handle.net/10919/64704en
dc.description.abstractThis thesis is concerned with the use of memory function devices in place of binary storage devices in sequential machines. In particular, various counters are considered as memory elements. Design limitations and design procedures for each type of counter are determined, with emphasis placed on UP/DN/PRESET type counters. It is shown that a presettable counter is capable of realizing any sequential machine. Special considerations involved in state assignment and minimization in designs using counters are investigated. Finally, extensions and areas of possible further study are discussed.en
dc.format.extent45 leavesen
dc.format.mimetypeapplication/pdfen
dc.language.isoen_USen
dc.publisherVirginia Polytechnic Institute and State Universityen
dc.relation.isformatofOCLC# 21651719en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1974.S35en
dc.subject.lcshLogic designen
dc.subject.lcshMemoryen
dc.titleSequential logic design using counters as memory elementsen
dc.typeThesisen
dc.contributor.departmentElectrical Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical Engineeringen
dc.type.dcmitypeTexten


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