Efficient Binary Field Multiplication on a VLIW DSP
dc.contributor.author | Tergino, Christian Sean | en |
dc.contributor.committeechair | Schaumont, Patrick R. | en |
dc.contributor.committeemember | Hsiao, Michael S. | en |
dc.contributor.committeemember | Feng, Wu-chun | en |
dc.contributor.department | Electrical and Computer Engineering | en |
dc.date.accessioned | 2014-03-14T20:40:22Z | en |
dc.date.adate | 2009-07-08 | en |
dc.date.available | 2014-03-14T20:40:22Z | en |
dc.date.issued | 2009-06-18 | en |
dc.date.rdate | 2009-07-08 | en |
dc.date.sdate | 2009-06-22 | en |
dc.description.abstract | Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM. | en |
dc.description.degree | Master of Science | en |
dc.identifier.other | etd-06222009-150103 | en |
dc.identifier.sourceurl | http://scholar.lib.vt.edu/theses/available/etd-06222009-150103/ | en |
dc.identifier.uri | http://hdl.handle.net/10919/33693 | en |
dc.publisher | Virginia Tech | en |
dc.relation.haspart | Thesis.pdf | en |
dc.rights | In Copyright | en |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
dc.subject | Very Long Instruction Word | en |
dc.subject | Modular Multiplication | en |
dc.subject | C64x+ | en |
dc.subject | Digital Signal Processor | en |
dc.subject | Multiplication | en |
dc.subject | Binary Field | en |
dc.subject | Galois Field | en |
dc.subject | GF | en |
dc.subject | Heterogeneous Multiprocessors | en |
dc.title | Efficient Binary Field Multiplication on a VLIW DSP | en |
dc.type | Thesis | en |
thesis.degree.discipline | Electrical and Computer Engineering | en |
thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
thesis.degree.level | masters | en |
thesis.degree.name | Master of Science | en |
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