A reliability comparison of recessed-gate and self-aligned gate small signal GaAs MESFETS utilizing an accelerated life test set designed for large scale automated testing
| dc.contributor.author | Rucker, Paul D. | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2016-05-23T17:53:57Z | en |
| dc.date.available | 2016-05-23T17:53:57Z | en |
| dc.date.issued | 1987 | en |
| dc.description.abstract | A large scale automated test set was designed and built to address the varied accelerated life test requirements of the GaAs industry. GaAs low-noise/small-signal MESFETs with 1 x 300 micron gate peripheries and 3 different gate structures were subjected to a 1000 hour high temperature storage test: 1) to compare the reliability performance and manufacturability of a) recessed-gate MESFETs with TiPdAu gates b) realigned self-aligned gate (RSAG) MESFETs with TiWN<sub>x</sub> Schottky and TiPdAu overlay c) planarized self-aligned gate (PSAG) MESFETs with TiWN<sub>x</sub> Schottky and TiPdAu overlay. 2) to study the changes in I<sub>dss</sub>, R<sub>g</sub>, R<sub>o</sub>, g<sub>m</sub>, and V<sub>p</sub> over time and their effects upon MAG (Maximum Available Gain). 3) to study failure criteria and their applicability toward accurate life predictions. The recessed-gate devices suffered from Au/GaAs channel interdiffusion resulting in substantial dc parameter degradation above 225°C with an activation energy of 1.7 eV. Although the most widely used device structure in the GaAs industry, its process is not conducive to parameter uniformity. The realigned self-aligned gate (RSAG) devices are an initial attempt at the fabrication of a self-aligned gate analog MESFET. They were found to exhibit excellent electrical characteristics, but their reliability performance was unpredictable due to the critical nature of the .5 micron TiPdAu gate overlay realignment to a 1 micron TiWN<sub>x</sub> Schottky. Planarized self-aligned gate (PSAG) devices were found to be readily manufacturable and to exhibit excellent reliability. The use of a decrease in MAG was found to be a more meaningful failure criterion than a 20% change in I<sub>dss</sub>, which is employed extensively in the literature. | en |
| dc.description.degree | Master of Science | en |
| dc.format.extent | xi, 109 leaves | en |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | http://hdl.handle.net/10919/71231 | en |
| dc.language.iso | en_US | en |
| dc.publisher | Virginia Polytechnic Institute and State University | en |
| dc.relation.isformatof | OCLC# 16655845 | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.lcc | LD5655.V855 1987.R83 | en |
| dc.subject.lcsh | Field-effect transistors | en |
| dc.subject.lcsh | Ion implantation | en |
| dc.title | A reliability comparison of recessed-gate and self-aligned gate small signal GaAs MESFETS utilizing an accelerated life test set designed for large scale automated testing | en |
| dc.type | Thesis | en |
| dc.type.dcmitype | Text | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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