Model Development, Synthesis and Validation Using the Modeler's Assistant

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dc.contributor.authorNarnur, Soumyaen
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberHa, Dong Samen
dc.contributor.committeememberGray, Festus Gailen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:43:21Zen
dc.date.adate1999-08-14en
dc.date.available2014-03-14T20:43:21Zen
dc.date.issued1999-08-06en
dc.date.rdate2000-08-14en
dc.date.sdate1999-08-12en
dc.description.abstractThis thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-081299-184716en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-081299-184716/en
dc.identifier.urihttp://hdl.handle.net/10919/34500en
dc.publisherVirginia Techen
dc.relation.haspartetd2.pdfen
dc.relation.haspartetd1.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSynthesisen
dc.subjectValidationen
dc.subjectVHDL Modelingen
dc.titleModel Development, Synthesis and Validation Using the Modeler's Assistanten
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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