A Synchronous Distributed Digital Control Architecture for High Power Converters

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dc.contributor.authorFrancis, Geralden
dc.contributor.committeechairBoroyevich, Dushanen
dc.contributor.committeememberTranter, William H.en
dc.contributor.committeememberKachroo, Pushkinen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:34:21Zen
dc.date.adate2005-05-17en
dc.date.available2014-03-14T20:34:21Zen
dc.date.issued2004-03-03en
dc.date.rdate2012-11-19en
dc.date.sdate2005-04-26en
dc.description.abstractPower electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control. This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-04262005-133303en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-04262005-133303/en
dc.identifier.urihttp://hdl.handle.net/10919/31942en
dc.publisherVirginia Techen
dc.relation.haspartJF_THESIS_RELEASE_N.pdfen
dc.relation.haspartUCSchematics.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectUniversal Controlleren
dc.subjectPower Electronicsen
dc.subjectSynchronous Communication Networksen
dc.subjectPlug and Playen
dc.subjectFiber Opticsen
dc.subjectDigital Control Systemsen
dc.subjectAEPSen
dc.subjectPower Electronics Building Blocks (PEBB)en
dc.subjectDSPen
dc.subjectField programmable gate arraysen
dc.subjectElectric Shipen
dc.subjectElectric Drivesen
dc.titleA Synchronous Distributed Digital Control Architecture for High Power Convertersen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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