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Characterizing Retention behavior of DDR4 SoDIMM

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dc.contributor.authorPalani, Purushothamanen
dc.contributor.committeechairXiong, Wenjieen
dc.contributor.committeememberNazhandali, Leylaen
dc.contributor.committeememberShao, Linboen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2024-06-06T08:03:23Zen
dc.date.available2024-06-06T08:03:23Zen
dc.date.issued2024-06-05en
dc.description.abstractgeneralWe are in an ever-increasing demand for computing power to sustain our technological advancements. A significant driving factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. Since the capacitors are prone to charge leakage, each bit must be frequently rewritten with its old value. A dedicated memory controller handles the periodic refreshes. If the cells aren't refreshed, the bits lose their charge and lose the information stored by flipping to either 0 or 1 (depending upon the design). Due to manufacturing variations, every tiny capacitor fabricated will have different physical characteristics. Charge leakage depends upon capacitance and other such physical properties. Hence, no two DRAM modules can have the same properties and decay pattern and cannot be reproduced again accurately. This DRAM attribute can be considered a source of 'Physically Unclonable Functions' and is sought after in the Cryptography domain. This thesis aims to characterize the decay patterns of commercial DDR4 DRAM modules. I implemented a custom System On Chip on AMD/Xilinx's ZCU104 FPGA platform to interface different DDR4 modules with a primitive memory controller (without refreshes). Additionally, I introduced electric and magnetic fields close to the DRAM module to investigate their effects on the decay characteristics.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.othervt_gsexam:40727en
dc.identifier.urihttps://hdl.handle.net/10919/119322en
dc.language.isoenen
dc.publisherVirginia Techen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectDDR4en
dc.subjectDRAMen
dc.subjectPUFen
dc.subjectFPGAen
dc.subjectXilinxen
dc.subjectMagnetic Fielden
dc.subjectdecayen
dc.subjectretention analysisen
dc.subjectbit flipsen
dc.titleCharacterizing Retention behavior of DDR4 SoDIMMen
dc.typeThesisen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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