Automatic back annotation of timing into VHDL behavioral models

Abstract

This thesis presents a design system that significantly speeds up development of VHDL behavioral models with back annotated timing. The behavioral model is developed using the CAD tool called Modeler's Assistant by inputting the model in the form of a Process Model Graph. Then using the built-in primitive process library and user responses the Modeler's Assistant generates a complete VHDL source description of the model. The models developed can be classified into four classes. The first class of circuits are combinational fanout free circuits in which the fanout of each process in the Process Model Graph is one. Combinational circuits in which outputs of the processes are fed in as input to more than one process are classified as Class 2 circuits. Sequential register circuits are classified as class 3 circuits. Class 4 circuits are highly sequential circuits which have either feedback loops or irregular register or flip-flop structures. The principle for back annotating the generic delay values is discussed for the first three classes of circuits. The back annotation tool Backann2 uses the VHDL description from the Modelers Assistant, the CLSI -VTIP CAD tool and the Synopsys Design Compiler to calculate the timing delays and to back annotate the delays into the behavioral model. The CLSI -VTIP tool is used to extract the details from the VHDL model and store it in the form of data structures. These details are used for computing the paths traversed by the signals associated with the generics. The behavioral model is synthesized into a gate level design and the end to end delays in the model are obtained using Synopsys Design Compiler. With the end to end delays and the different paths traversed by the signals an algorithm to find realistic and accurate delays has been found. Thus a system is available to designers which builds behavioral models with accurate timing information.