Output Capacitance Loss Measurement and Validation for Low-Voltage Silicon and GaN Devices in DC-DC Converter Applications

With the rise of soft-switched converter topologies which enable high-frequency power conversion, there has been a premise that these converter topologies can help achieve loss-less switching in a power device. However, this theory is not completely true as there even with soft-switching there is some degree of loss associated in the form of output capacitance-related hysteresis loss, channel turn-off loss, and loss during the dead-time period in these converter topologies. The soft-switching converters utilize the existence of the device's output capacitance (COSS), which is charged and discharged consecutively at each switching cycle, and a hysteresis loss exists due to the difference in charging and discharging output capacitance. In order fully utilize the potential of these novel soft-switching topologies, we need to investigate further into the origins of these losses or loss mechanisms, methods to measure or compute these losses, and then devise ways to optimize the loss for a given application. This work focuses on exploring methods to quantify this loss for different operating conditions like device current, switching frequency, dV/dT, etc. In this aspect, some methods have been studied and used to quantify this hysteresis loss for a variety of power devices like SI and GaN. It is reported that only channel turn-off losses exist in devices with ZVS transition, however, we found that the charging and discharging of COSS is not loss-free and thus it is important that we account for this loss in the design process. Finally, the loss data obtained from these tests are compared with each other for five different power devices to validate their applicability, and later these test results are used to get an optimized device selection criterion for the best possible efficiency and minimal losses for a ZVS application.